GPU: Added TIC and TSC registers to the Maxwell3D register structure.

Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)

vi: TransactParcel DequeueBuffer should wait current thread

GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.

This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.

GPU: Handle writes to the CB_DATA method.

This macro binds the SSBO Info Buffer as the current ConstBuffer.
This buffer is usually bound to c0 during shader execution.
Games seem to use this macro instead of directly writing the address for some reason.

Writing to this method will cause the written value to be stored in the currently-set ConstBuffer plus CB_POS.

This method is usually used to upload uniforms or other shader-visible data.

This should reduce recompile times when editing the Maxwell3D register structure.

 GPU: Store uploaded GPU macros and keep track of the number of method arguments.

 GPU: Store shader constbuffer bindings in the GPU state. 

It'll now set the CB_SIZE, CB_ADDRESS and CB_BIND registers when it's called.

Presumably this SetShader function is binding the constant shader uniforms to buffer 1 (c1[]).

Register 0xE24 is actually a macro that sets some shader parameters in the register structure.

Macros are uploaded to the GPU at startup and have their own ISA, we'll probably write an interpreter for this in the future.

GPU: Handle the SetShader method call (0xE24) and store the shader config.

GPU: Added the vertex array registers.

GPU: Process command mode 5 (IncreaseOnce) differently from other commands

Accumulate all arguments before calling the desired method.

Note: Maybe we should do the same for the NonIncreasing mode?

GPU: Added some shader-related registers.

nvflinger: Remove superfluous buffer format check.

Shader address calculation depends on this value to some extent, we do not currently know what it being 0 entails.

Various heap fixes for libtransistor