- Mar 21, 2018
- Mar 20, 2018
- Mar 19, 2018
-
-
Subv authored
-
Subv authored
-
bunnei authored
Implement Pull #3064 from citra: Clean all format warnings (Yuzu-specific format warnings cleared too)
-
N00byKing authored
-
N00byKing authored
-
N00byKing authored
-
N00byKing authored
-
bunnei authored
GPU: Added TIC and TSC registers to the Maxwell3D register structure.
-
Subv authored
-
Subv authored
-
bunnei authored
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
-
bunnei authored
vi: TransactParcel DequeueBuffer should wait current thread
-
bunnei authored
GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.
-
bunnei authored
-
bunnei authored
-
bunnei authored
-
bunnei authored
-
bunnei authored
-
Subv authored
This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.
-
- Mar 18, 2018
-
-
bunnei authored
GPU: Handle writes to the CB_DATA method.
-
Subv authored
This macro binds the SSBO Info Buffer as the current ConstBuffer. This buffer is usually bound to c0 during shader execution. Games seem to use this macro instead of directly writing the address for some reason.
-
Subv authored
Writing to this method will cause the written value to be stored in the currently-set ConstBuffer plus CB_POS. This method is usually used to upload uniforms or other shader-visible data.
-
Subv authored
This should reduce recompile times when editing the Maxwell3D register structure.
-
Sebastian Valle authored
GPU: Store uploaded GPU macros and keep track of the number of method arguments.
-