- 21 Mar, 2018 7 commits
- 20 Mar, 2018 12 commits
- 19 Mar, 2018 19 commits
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Subv authored
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Subv authored
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bunnei authored
Implement Pull #3064 from citra: Clean all format warnings (Yuzu-specific format warnings cleared too)
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N00byKing authored
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N00byKing authored
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N00byKing authored
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N00byKing authored
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bunnei authored
GPU: Added TIC and TSC registers to the Maxwell3D register structure.
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Subv authored
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Subv authored
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bunnei authored
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
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bunnei authored
vi: TransactParcel DequeueBuffer should wait current thread
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bunnei authored
GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.
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bunnei authored
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bunnei authored
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bunnei authored
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bunnei authored
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bunnei authored
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Subv authored
This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.
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- 18 Mar, 2018 2 commits