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Commit e7dfcdde authored by Subv's avatar Subv
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GPU: Corrected the branch targets for the shader bra instruction.

parent 8c99dd05
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...@@ -328,15 +328,16 @@ union Instruction { ...@@ -328,15 +328,16 @@ union Instruction {
} texs; } texs;
union { union {
BitField<20, 5, u64> target; BitField<20, 24, u64> target;
BitField<5, 1, u64> constant_buffer; BitField<5, 1, u64> constant_buffer;
s32 GetBranchTarget() const { s32 GetBranchTarget() const {
// Sign extend the branch target offset // Sign extend the branch target offset
u32 mask = 1U << (5 - 1); u32 mask = 1U << (24 - 1);
u32 value = static_cast<u32>(target); u32 value = static_cast<u32>(target);
// The branch offset is relative to the next instruction, so add 1 to it. // The branch offset is relative to the next instruction and is stored in bytes, so
return static_cast<s32>((value ^ mask) - mask) + 1; // divide it by the size of an instruction and add 1 to it.
return static_cast<s32>((value ^ mask) - mask) / sizeof(Instruction) + 1;
} }
} bra; } bra;
......
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