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Commit 5ac2a41f authored by bunnei's avatar bunnei
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Merge pull request #669 from lioncash/cruft

armmmu: Remove unnecessary enum values
parents 1981aa3d f23f2a9a
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......@@ -26,36 +26,26 @@
// Register numbers in the MMU
enum
{
MMU_ID = 0,
MMU_CONTROL = 1,
MMU_TRANSLATION_TABLE_BASE = 2,
MMU_DOMAIN_ACCESS_CONTROL = 3,
MMU_FAULT_STATUS = 5,
MMU_FAULT_ADDRESS = 6,
MMU_CACHE_OPS = 7,
MMU_TLB_OPS = 8,
MMU_CACHE_LOCKDOWN = 9,
MMU_TLB_LOCKDOWN = 10,
MMU_PID = 13,
// MMU_V4
MMU_V4_CACHE_OPS = 7,
MMU_V4_TLB_OPS = 8,
// MMU_V3
MMU_V3_FLUSH_TLB = 5,
MMU_V3_FLUSH_TLB_ENTRY = 6,
MMU_V3_FLUSH_CACHE = 7,
// MMU Intel SA-1100
MMU_SA_RB_OPS = 9,
MMU_SA_DEBUG = 14,
MMU_SA_CP15_R15 = 15,
// Intel xscale CP15
XSCALE_CP15_CACHE_TYPE = 0,
XSCALE_CP15_AUX_CONTROL = 1,
XSCALE_CP15_COPRO_ACCESS = 15,
MMU_ID = 0,
MMU_CONTROL = 1,
MMU_TRANSLATION_TABLE_BASE = 2,
MMU_DOMAIN_ACCESS_CONTROL = 3,
MMU_FAULT_STATUS = 5,
MMU_FAULT_ADDRESS = 6,
MMU_CACHE_OPS = 7,
MMU_TLB_OPS = 8,
MMU_CACHE_LOCKDOWN = 9,
MMU_TLB_LOCKDOWN = 10,
MMU_PID = 13,
// MMU_V4
MMU_V4_CACHE_OPS = 7,
MMU_V4_TLB_OPS = 8,
// MMU_V3
MMU_V3_FLUSH_TLB = 5,
MMU_V3_FLUSH_TLB_ENTRY = 6,
MMU_V3_FLUSH_CACHE = 7,
};
// Reads data in big/little endian format based on the
......
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