From cff7b29bbaca20b28ea52eedefed7c1cdafff2b9 Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 19 Mar 2018 00:32:57 -0500
Subject: [PATCH] GPU: Added the TIC registers to the Maxwell3D register
structure.
---
src/video_core/engines/maxwell_3d.h | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 5d9b0043b7..272ebee311 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -62,7 +62,21 @@ public:
union {
struct {
- INSERT_PADDING_WORDS(0x582);
+ INSERT_PADDING_WORDS(0x55D);
+
+ struct {
+ u32 tic_address_high;
+ u32 tic_address_low;
+ u32 tic_limit;
+
+ GPUVAddr TICAddress() const {
+ return static_cast<GPUVAddr>(
+ (static_cast<GPUVAddr>(tic_address_high) << 32) | tic_address_low);
+ }
+ } tic;
+
+ INSERT_PADDING_WORDS(0x22);
+
struct {
u32 code_address_high;
u32 code_address_low;
@@ -264,6 +278,7 @@ private:
static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
"Field " #field_name " has invalid position")
+ASSERT_REG_POSITION(tic, 0x55D);
ASSERT_REG_POSITION(code_address, 0x582);
ASSERT_REG_POSITION(draw, 0x585);
ASSERT_REG_POSITION(query, 0x6C0);
--
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