From acdbbb88854b4c1dc75353018fcf2e5480cea858 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Fri, 21 Dec 2018 02:08:52 -0300
Subject: [PATCH] shader_decode: Implement LD_C
---
src/video_core/shader/decode/memory.cpp | 31 +++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index d8265d3fdc..6219f8ee69 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -73,6 +73,37 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
}
break;
}
+ case OpCode::Id::LD_C: {
+ UNIMPLEMENTED_IF(instr.ld_c.unknown != 0);
+
+ Node index = GetRegister(instr.gpr8);
+
+ const Node op_a =
+ GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 0, index);
+
+ switch (instr.ld_c.type.Value()) {
+ case Tegra::Shader::UniformType::Single:
+ SetRegister(bb, instr.gpr0, op_a);
+ break;
+
+ case Tegra::Shader::UniformType::Double: {
+ const Node op_b =
+ GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
+
+ const Node composite =
+ Operation(OperationCode::Composite, op_a, op_b, GetRegister(RZ), GetRegister(RZ));
+
+ MetaComponents meta{{0, 1, 2, 3}};
+ bb.push_back(Operation(OperationCode::AssignComposite, meta, composite,
+ GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
+ GetRegister(RZ), GetRegister(RZ)));
+ break;
+ }
+ default:
+ UNIMPLEMENTED_MSG("Unhandled type: {}", static_cast<unsigned>(instr.ld_c.type.Value()));
+ }
+ break;
+ }
case OpCode::Id::ST_A: {
UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
"Indirect attribute loads are not supported");
--
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