From a7b5ab4d9a275c6a16c5a7fdb2fd39827922eb61 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Thu, 26 Apr 2018 23:21:17 -0400
Subject: [PATCH] gl_shader_decompiler: Implement MOV32_IMM instruction.

---
 src/video_core/engines/shader_bytecode.h                | 4 ++--
 src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index f3ca30cfaa..fba9ab4961 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -290,7 +290,7 @@ public:
         MOV_C,
         MOV_R,
         MOV_IMM,
-        MOV32I,
+        MOV32_IMM,
         SHR_C,
         SHR_R,
         SHR_IMM,
@@ -445,7 +445,7 @@ private:
             INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
             INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
             INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
-            INST("000000010000----", Id::MOV32I, Type::Arithmetic, "MOV32I"),
+            INST("000000010000----", Id::MOV32_IMM, Type::Arithmetic, "MOV32_IMM"),
             INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
             INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
             INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 8b235e252f..647da4eb08 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -620,6 +620,11 @@ private:
             }
 
             switch (opcode->GetId()) {
+            case OpCode::Id::MOV32_IMM: {
+                // mov32i doesn't have abs or neg bits.
+                regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1);
+                break;
+            }
             case OpCode::Id::FMUL_C:
             case OpCode::Id::FMUL_R:
             case OpCode::Id::FMUL_IMM: {
-- 
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