From a2819c204f1a72a63ee5e8cc9a9830cd27fb6853 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Fri, 21 Dec 2018 02:05:52 -0300
Subject: [PATCH] shader_decode: Implement SHR
---
src/video_core/shader/decode/shift.cpp | 27 +++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/src/video_core/shader/decode/shift.cpp b/src/video_core/shader/decode/shift.cpp
index 41f5b8cb04..76938fa05f 100644
--- a/src/video_core/shader/decode/shift.cpp
+++ b/src/video_core/shader/decode/shift.cpp
@@ -16,7 +16,32 @@ u32 ShaderIR::DecodeShift(BasicBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
- UNIMPLEMENTED();
+ const Node op_a = GetRegister(instr.gpr8);
+ const Node op_b = [&]() {
+ if (instr.is_b_imm) {
+ return Immediate(instr.alu.GetSignedImm20_20());
+ } else if (instr.is_b_gpr) {
+ return GetRegister(instr.gpr20);
+ } else {
+ return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
+ }
+ }();
+
+ switch (opcode->get().GetId()) {
+ case OpCode::Id::SHR_C:
+ case OpCode::Id::SHR_R:
+ case OpCode::Id::SHR_IMM: {
+ UNIMPLEMENTED_IF_MSG(instr.generates_cc,
+ "Condition codes generation in SHR is not implemented");
+
+ const Node value = SignedOperation(OperationCode::IArithmeticShiftRight,
+ instr.shift.is_signed, PRECISE, op_a, op_b);
+ SetRegister(bb, instr.gpr0, value);
+ break;
+ }
+ default:
+ UNIMPLEMENTED_MSG("Unhandled shift instruction: {}", opcode->get().GetName());
+ }
return pc;
}
--
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