From 9ece9da50d7c7827b9eb3bb9cfb007fb4af07061 Mon Sep 17 00:00:00 2001
From: bunnei <ericbunnie@gmail.com>
Date: Thu, 5 Jun 2014 00:20:11 -0400
Subject: [PATCH] arm: fixed bug in how thread context switch occurs with
SkyEye
---
src/core/arm/interpreter/arm_interpreter.cpp | 7 +++++--
src/core/hle/svc.h | 4 ++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 2aa100e86d..8030ec56a2 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -118,6 +118,9 @@ void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
ctx.fpscr = state->VFP[1];
ctx.fpexc = state->VFP[2];
+
+ ctx.reg_15 = state->Reg[15];
+ ctx.mode = state->NextInstr;
}
/**
@@ -137,8 +140,8 @@ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
state->VFP[1] = ctx.fpscr;
state->VFP[2] = ctx.fpexc;
- state->Reg[15] = ctx.pc;
- state->NextInstr = RESUME;
+ state->Reg[15] = ctx.reg_15;
+ state->NextInstr = ctx.mode;
}
/// Prepare core for thread reschedule (if needed to correctly handle state)
diff --git a/src/core/hle/svc.h b/src/core/hle/svc.h
index c5170aab79..1d125faf62 100644
--- a/src/core/hle/svc.h
+++ b/src/core/hle/svc.h
@@ -29,6 +29,10 @@ struct ThreadContext {
u32 fpu_registers[32];
u32 fpscr;
u32 fpexc;
+
+ // These are not part of native ThreadContext, but needed by emu
+ u32 reg_15;
+ u32 mode;
};
enum ResetType {
--
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