From 5f4ee6f0c8c7b2532bc5be841fcee4670495d7f7 Mon Sep 17 00:00:00 2001
From: FernandoS27 <fsahmkow27@gmail.com>
Date: Tue, 9 Oct 2018 22:28:19 -0400
Subject: [PATCH] Add memory Layout to Render Targets and Depth Buffers
---
src/video_core/engines/maxwell_3d.h | 16 ++++++++--
.../renderer_opengl/gl_rasterizer_cache.cpp | 30 +++++++++----------
.../renderer_opengl/gl_rasterizer_cache.h | 8 ++---
3 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 896498b899..68831a1ac7 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -347,6 +347,16 @@ public:
DecrWrap = 8,
};
+ enum class MemoryLayout : u32 {
+ Linear = 0,
+ BlockLinear = 1,
+ };
+
+ enum class InvMemoryLayout : u32 {
+ BlockLinear = 0,
+ Linear = 1,
+ };
+
struct Cull {
enum class FrontFace : u32 {
ClockWise = 0x0900,
@@ -436,7 +446,8 @@ public:
BitField<0, 3, u32> block_width;
BitField<4, 3, u32> block_height;
BitField<8, 3, u32> block_depth;
- } block_dimensions;
+ BitField<12, 1, InvMemoryLayout> type;
+ } memory_layout;
u32 array_mode;
u32 layer_stride;
u32 base_layer;
@@ -556,7 +567,8 @@ public:
BitField<0, 4, u32> block_width;
BitField<4, 4, u32> block_height;
BitField<8, 4, u32> block_depth;
- } block_dimensions;
+ BitField<20, 1, InvMemoryLayout> type;
+ } memory_layout;
u32 layer_stride;
GPUVAddr Address() const {
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 433b34b272..65a220c411 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -99,10 +99,11 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
const auto& config{Core::System::GetInstance().GPU().Maxwell3D().regs.rt[index]};
SurfaceParams params{};
params.addr = TryGetCpuAddr(config.Address());
- params.is_tiled = true;
- params.block_width = 1 << config.block_dimensions.block_width;
- params.block_height = 1 << config.block_dimensions.block_height;
- params.block_depth = 1 << config.block_dimensions.block_depth;
+ params.is_tiled =
+ config.memory_layout.type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
+ params.block_width = 1 << config.memory_layout.block_width;
+ params.block_height = 1 << config.memory_layout.block_height;
+ params.block_depth = 1 << config.memory_layout.block_depth;
params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
params.component_type = ComponentTypeFromRenderTarget(config.format);
params.type = GetFormatType(params.pixel_format);
@@ -124,14 +125,13 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
return params;
}
-/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
- Tegra::GPUVAddr zeta_address,
- Tegra::DepthFormat format,
- u32 block_width, u32 block_height,
- u32 block_depth) {
+/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(
+ u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
+ u32 block_width, u32 block_height, u32 block_depth,
+ Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type) {
SurfaceParams params{};
params.addr = TryGetCpuAddr(zeta_address);
- params.is_tiled = true;
+ params.is_tiled = type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
params.block_width = 1 << std::min(block_width, 5U);
params.block_height = 1 << std::min(block_height, 5U);
params.block_depth = 1 << std::min(block_depth, 5U);
@@ -156,9 +156,9 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
SurfaceParams params{};
params.addr = TryGetCpuAddr(config.Address());
params.is_tiled = !config.linear;
- params.block_width = params.is_tiled ? std::min(config.BlockWidth(),32U) : 0,
- params.block_height = params.is_tiled ? std::min(config.BlockHeight(),32U) : 0,
- params.block_depth = params.is_tiled ? std::min(config.BlockDepth(),32U) : 0,
+ params.block_width = params.is_tiled ? std::min(config.BlockWidth(), 32U) : 0,
+ params.block_height = params.is_tiled ? std::min(config.BlockHeight(), 32U) : 0,
+ params.block_depth = params.is_tiled ? std::min(config.BlockDepth(), 32U) : 0,
params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
params.component_type = ComponentTypeFromRenderTarget(config.format);
params.type = GetFormatType(params.pixel_format);
@@ -1005,8 +1005,8 @@ Surface RasterizerCacheOpenGL::GetDepthBufferSurface(bool preserve_contents) {
SurfaceParams depth_params{SurfaceParams::CreateForDepthBuffer(
regs.zeta_width, regs.zeta_height, regs.zeta.Address(), regs.zeta.format,
- regs.zeta.block_dimensions.block_width, regs.zeta.block_dimensions.block_height,
- regs.zeta.block_dimensions.block_depth)};
+ regs.zeta.memory_layout.block_width, regs.zeta.memory_layout.block_height,
+ regs.zeta.memory_layout.block_depth, regs.zeta.memory_layout.type)};
return GetSurface(depth_params, preserve_contents);
}
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.h b/src/video_core/renderer_opengl/gl_rasterizer_cache.h
index 542886a6fc..66d98ad4e0 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.h
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.h
@@ -716,10 +716,10 @@ struct SurfaceParams {
static SurfaceParams CreateForFramebuffer(std::size_t index);
/// Creates SurfaceParams for a depth buffer configuration
- static SurfaceParams CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
- Tegra::GPUVAddr zeta_address,
- Tegra::DepthFormat format, u32 block_width,
- u32 block_height, u32 block_depth);
+ static SurfaceParams CreateForDepthBuffer(
+ u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
+ u32 block_width, u32 block_height, u32 block_depth,
+ Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type);
/// Creates SurfaceParams for a Fermi2D surface copy
static SurfaceParams CreateForFermiCopySurface(
--
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